1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More particularly, the invention relates to technology that can be effectively utilized for a semiconductor integrated circuit device having a clock-generating circuit for generating clock signals corresponding to clock signals supplied through an external terminals, and that can be effectively utilized chiefly for a synchronous dynamic RAM (random access memory).
2. Prior Art
As a semiconductor integrated circuit device having a digital circuit that operates on clock signals supplied through an external terminal, there has been known a DLL (delay locked loop) which is a circuit for bringing the clock signals supplied through the external terminal into synchronism with the internal clock signals to increase the frequency of the clock signals while preventing reduction in the timing margin caused by a delay relative to the clock signals supplied to the internal circuit. The DLL is constituted by a variable delay circuit for varying the amount of delay and a control circuit for controlling the amount of delay. The phase-synchronizing circuits have been disclosed in Japanese Patent Laid-Open Nos. 90666/1990, 55145/1999 and 171774/1998.
As a variable delay circuit for the DLL, there can be contrived a digital variable delay circuit for varying the amount of delay by changing over the number of stages of the circuit and an analog variable delay circuit for varying the amount of delay by changing the drive current to the delay element or by changing the load. As the circuit for controlling the amount of delay of the analog DLL by using the analog variable delay circuit, further, there can be contrived a circuit of the digital system that executes a digital control operation and a circuit of the analog system which uses a charge pump or the like. Performances of the DLLs based on the combinations of the circuits can be roughly classified as follows:
(1) Digital control digital DLL: consumes a large amount of power, precision is low, short lock-in cycle, intermediate immunity to noise.
(2) Digital control analog DLL: consumes a large amount of power, precision is high, short lock-in cycle, intermediate immunity to noise.
(3) Analog control analog DLL: consumes a small amount of power, precision is high, long lock-in cycle, poor immunity to noise.
The above-mentioned three kinds of DLLs have their features as described above, and an analog control analog DLL is arrived at if power consumption and precision are pursued. However, the analog control DLL has defects of a long lock-in cycle and relatively poor immunity to noise. Even in the digital control DLL, the variable delay circuit is affected by noise; i.e., immunity to noise is not so good, and improving this defect is meaningful. In the analog control circuit, the control circuit, too, is affected by noise and it is estimated that immunity to noise is poorer than that of the digital control circuit.
In a semiconductor integrated circuit device in which the internal digital circuit is operated by clock signals supplied through an external terminal as represented by a synchronous DRAM (dynamic random access memory), it is expected that input/output operation for the band width, i.e., for the data will be demanded in the future. Thus, there remains a room for improvement for the DLL of either system in connection with the precision, immunity to noise and lock-in cycle.
This invention provides a semiconductor integrated circuit device equipped with a DLL realizing a stable clock-generating operation. The invention further provides a semiconductor integrated circuit device equipped with a clock-generating circuit that uses a DLL of a high precision and of a low power consumption. The invention further provides a semiconductor integrated circuit device equipped with a clock-generating circuit constituted by using a DLL which shortens the lock-in cycle yet maintaining a high precision and consuming a small amount of electric power. The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the accompanying drawings.
Representative examples of the invention disclosed in this application will now be briefly described. That is, the invention is concerned with a clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology.
Another representative example of the invention disclosed in this application will be briefly described next.
That is, the invention is concerned with a clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an operation voltage is applied to the clock-generating circuit by using a dedicated bonding pad and a lead different from those of the power source passage that applies an operation voltage to the internal circuit.
A further representative example of the invention disclosed in this application will be briefly described next.
That is, the invention is concerned with a clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the control circuit so controls the variable delay circuit as to return the amount of delay back in the reverse direction at a moment when the variable delay time has exceeded a target value.